Most digital circuits designed and fabricated today are “synchronous.” In essence, synchronous circuits are based on two fundamental assumptions that greatly simplify their design: (1) all signals are binary, and (2) all components share a common and discrete notion of time, as defined by a clock signal distributed throughout the circuit.
Asynchronous circuits are fundamentally different. They also assume binary signals, but there is no common and discrete time. Instead the circuits use handshaking between their components in order to perform the necessary synchronization, communication, and sequencing of operations. Expressed in terms usually used with regard to synchronous circuits this results in a behaviour that is similar to a systematic fine-grain clock gating and local clocks that are not in phase and whose periods are determined by actual circuit delays. This difference gives asynchronous circuits inherent properties that may be advantageous (with respect to, e.g., power consumption, operating speed, electromagnetic emission, robustness towards variations in supply voltage, temperature, fabrication process parameters, etc.) as compared to synchronous (clocked) circuits.
On the other hand there are also some drawbacks. Asynchronous circuits usually require a control logic for implementing handshake operations that are necessary to synchronize different circuit elements as a global clock signal does not exist. The asynchronous control logic that implements the handshaking normally represents an overhead in terms of circuit complexity.
Important handshaking components that are commonly used to implement the mentioned handshake operations require that the communication along several (input) channels is mutually exclusive, at least at a point at which two channels are merged into a common channel (see, e.g., Jens Sparsø, ed.: Section 5.8 “Mutual exclusion, arbitration and metastability,” in: PRINCIPLES OF ASYNCHRONOUS CIRCUIT DESIGN—A Systems Perspective, Kluwer Academic Publishers, 2001). That is, a high-low transition (or vice versa) may only occur in one single channel at a given time. Simultaneous “events” in two or more channels are usually handled by arbiters that use so-called mutex elements to decide which event to process first. However, mutex elements are subject to undesired metastability effects when two events occur simultaneously or almost simultaneously (i.e., within a short time interval).
Particularly when implementing finite state machines (FSMs) concurrently occurring events in different communication channels (e.g., on different signalling lines) may be problematic and appropriate arbitration circuits (arbiters) may be significantly complex. There is a need for an easy-to-synthesize state machine including an arbiter for handling concurrent events in different communication channels.